From 3bcf563fec26378f7f4cf1e2ad0d4d5b3f341919 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Mon, 2 Mar 2015 11:09:35 +0000 Subject: [PATCH] xen: arm: Assume level triggered means high, not low. When reading back the ICFG register we cannot know the polarity of the configuration, just that it is level or edge. Since falling edge and low level are invalid for SPIs we should assume rising edge and high level (we have no better information for PPIs, so it'll have to do). We already assumed rising edge, switch to high level as well. Signed-off-by: Ian Campbell Reviewed-by: Julien Grall --- xen/arch/arm/gic-v2.c | 2 +- xen/arch/arm/gic-v3.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 3e141c4624..20cdbc9b48 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -240,7 +240,7 @@ static void gicv2_set_irq_properties(struct irq_desc *desc, actual & edgebit ? "Edge" : "Level"); desc->arch.type = actual & edgebit ? DT_IRQ_TYPE_EDGE_RISING : - DT_IRQ_TYPE_LEVEL_LOW; + DT_IRQ_TYPE_LEVEL_HIGH; } /* Set target CPU mask (RAZ/WI on uniprocessor) */ diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 66cc2a2c2e..ab806701dd 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -504,7 +504,7 @@ static void gicv3_set_irq_properties(struct irq_desc *desc, actual & edgebit ? "Edge" : "Level"); desc->arch.type = actual & edgebit ? DT_IRQ_TYPE_EDGE_RISING : - DT_IRQ_TYPE_LEVEL_LOW; + DT_IRQ_TYPE_LEVEL_HIGH; } affinity = gicv3_mpidr_to_affinity(cpu); -- 2.30.2